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 a
FEATURES Ultrahigh Speed 5,500 V/ s Slew Rate, 4 V Step, G = +2 545 ps Rise Time, 2 V Step, G = +2 Large Signal Bandwidth 440 MHz, G = +2 320 MHz, G = +10 Small Signal Bandwidth (-3 dB) 1 GHz, G = +1 700 MHz, G = +2 Settling Time 10 ns to 0.1%, 2 V Step, G = +2 Low Distortion Over Wide Bandwidth SFDR -44 dBc @ 150 MHz, G = +2, VO = 2 V p-p -41 dBc @ 150 MHz, G = +10, VO = 2 V p-p 3rd Order Intercept (3IP) 26 dBm @ 70 MHz, G = +10 18 dBm @ 150 MHz, G = +10 Good Video Specifications Gain Flatness 0.1 dB to 75 MHz 0.01% Differential Gain Error, RL = 150 0.01 Differential Phase Error, RL = 150 High Output Drive 175 mA Output Load Drive 10 dBm with -38 dBc SFDR @ 70 MHz, G = +10 Supply Operation 5 V Voltage Supply 14 mA (Typ) Supply Current APPLICATIONS Pulse Amplifier IF/RF Gain Stage/Amplifiers High Resolution Video Graphics High Speed Instrumentations CCD Imaging Amplifier
2 1 0 G = +2 RF = 301 RL = 150
1 GHz, 5,500 V/ s Low Distortion Amplifier AD8009
FUNCTIONAL BLOCK DIAGRAM 8-Lead Plastic SOIC (SO-8)
NC 1 -IN 2 +IN 3 -VS 4 NC = NO CONNECT
5-Lead SOT-23 (RT-5)
AD8009
VOUT 1 -VS 2 +IN 3
4 5
AD8009
8
NC
7 +VS 6 5 OUT NC
+VS
-IN
PRODUCT DESCRIPTION The AD8009 is an ultrahigh speed current feedback amplifier with a phenomenal 5,500 V/s slew rate that results in a rise time of 545 ps, making it ideal as a pulse amplifier. The high slew rate reduces the effect of slew rate limiting and results in the large signal bandwidth of 440 MHz required for high resolution video graphic systems. Signal quality is maintained over a wide bandwidth with worst case distortion of -40 dBc @ 250 MHz (G = +10, 1 V p-p). For applications with multitone signals such as IF signal chains, the third order Intercept (3IP) of 12 dBm is achieved at the same frequency. This distortion performance coupled with the current feedback architecture make the AD8009 a flexible component for a gain stage amplifier in IF/RF signal chains. The AD8009 is capable of delivering over 175 mA of load current and will drive four back terminated video loads while maintaining low differential gain and phase error of 0.02% and 0.04 respectively. The high drive capability is also reflected in the ability to deliver 10 dBm of output power @ 70 MHz with -38 dBc SFDR. The AD8009 is available in a small SOIC package and will operate over the industrial temperature range -40C to +85C.
-30 G=2 RF = 301 VO = 2V p-p 100 2ND, LOAD 3RD, 100 LOAD -80 3RD, 150 LOAD -90 2ND, LOAD
-40
NORMALIZED GAIN - dB
VO = 2Vp-p -2 -3 -4 -5 -6 -7 -8
G = +10 RF = 200 RL = 100
DISTORTION - dBc
-1
-50 -60 150 -70
-100 1 100 10 FREQUENCY RESPONSE - MHz 1000 1 10 FREQUENCY RESPONSE - MHz 100 200
Figure 1. Large Signal Frequency Response; G = +2 & +10
Figure 2. Distortion vs. Frequency; G = +2
REV. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 2000
= V = R R 301 for G = AD8009-SPECIFICATIONSfor(@=T +1,+25=C,226 = for5 V, =R +2 100 R ,=for191Package:+10,=unless otherwise+1, +2, R = 200 for G = +10, for RT Package: R = 332 G R G and for G = noted.)
A S L F F F F F
Model DYNAMIC PERFORMANCE -3 dB Small Signal Bandwidth, VO = 0.2 V p-p R Package RT Package
Conditions
Min
AD8009AR Typ
Max
Units
Large Signal Bandwidth, VO = 2 V p-p Gain Flatness 0.1 dB, VO = 0.2 V p-p Slew Rate Settling Time to 0.1% Rise and Fall Time HARMONIC/NOISE PERFORMANCE SFDR G = +2, VO = 2 V p-p SFDR G = +10, VO = 2 V p-p Third Order Intercept (3IP) W.R.T. Output, G = +10 Input Voltage Noise Input Current Noise Differential Gain Error Differential Phase Error DC PERFORMANCE Input Offset Voltage
G = +1, RF = 301 G = +1, RF = 332 G = +2 G = +10 G = +2 G = +10 G = +2, RL = 150 G = +2, RL = 150 , 4 V Step G = +2, RL = 150 , 2 V Step G = +10, 2 V Step G = +2, RL = 150 , 4 V Step 5 MHz 70 MHz 150 MHz 5 MHz 70 MHz 150 MHz 70 MHz 150 MHz 250 MHz f = 10 MHz f = 10 MHz, +In f = 10 MHz, -In NTSC, G = +2, RL = 150 NTSC, G = +2, RL = 37.5 NTSC, G = +2, RL = 150 NTSC, G = +2, RL = 37.5
480 300 390 235 45 4500
1000 845 700 350 440 320 75 5500 10 25 0.725 -74 -53 -44 -58 -41 -41 26 18 12 1.9 46 41 0.01 0.02 0.01 0.04 2
MHz MHz MHz MHz MHz MHz MHz V/s ns ns ns dBc dBc dBc dBc dBc dBc dBm dBm dBm nV/Hz pA/Hz pA/Hz % % Degrees Degrees mV mV V/C A A A A k k k pF V dB V mA mA 6 16 18 V mA mA dB
0.03 0.05 0.03 0.08 5 7 150 150
TMIN-TMAX Offset Voltage Drift -Input Bias Current TMIN-TMAX +Input Bias Voltage TMIN-TMAX Open Loop Transresistance TMIN-TMAX INPUT CHARACTERISTICS Input Resistance Input Capacitance Input Common-Mode Voltage Range Common-Mode Rejection Ratio OUTPUT CHARACTERISTICS Output Voltage Swing Output Current Short Circuit Current POWER SUPPLY Operating Range Quiescent Current Power Supply Rejection Ratio
Specifications subject to change without notice.
90
4 50 75 50 75 250 170 110 8 2.6 3.8 52 3.8 175 330
+Input -Input +Input VCM = 2.5 50
3.7 RL = 10 , PD Package = 0.7 W 150
4 14 TMIN-TMAX VS = 4 V to 6 V 64 70
-2-
REV. B
AD8009
ABSOLUTE MAXIMUM RATINGS 1 MAXIMUM POWER DISSIPATION
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12.6 V Internal Power Dissipation2 Small Outline Package (R) . . . . . . . . . . . . . . . . . 0.75 Watts Input Voltage (Common Mode) . . . . . . . . . . . . . . . . . . . . VS Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . 3.5 V Output Short Circuit Duration . . . . . . . . . . . . . . . . . . . . . . Observe Power Derating Curves Storage Temperature Range R Package . . . . -65C to +125C Operating Temperature Range (A Grade) . . . -40C to +85C Lead Temperature Range (Soldering 10 sec) . . . . . . . . +300C
NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 Specification is for device in free air: 8-Lead SOIC Package: JA = 155C/W.
The maximum power that can be safely dissipated by the AD8009 is limited by the associated rise in junction temperature. The maximum safe junction temperature for plastic encapsulated devices is determined by the glass transition temperature of the plastic, approximately +150C. Exceeding this limit temporarily may cause a shift in parametric performance due to a change in the stresses exerted on the die by the package. Exceeding a junction temperature of +175C for an extended period can result in device failure. While the AD8009 is internally short circuit protected, this may not be sufficient to guarantee that the maximum junction temperature (+150C) is not exceeded under all conditions. To ensure proper operation, it is necessary to observe the maximum power derating curves.
2.0
MAXIMUM POWER DISSIPATION - Watts
TJ = +150C
1.5 8-LEAD SOIC PACKAGE 1.0
0.5 5-LEAD SOT-23 PACKAGE
0 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 AMBIENT TEMPERATURE - C
70 80 90
Figure 3. Plot of Maximum Power Dissipation vs. Temperature
ORDERING GUIDE
Model AD8009AR AD8009AR-REEL AD8009ART AD8009ART-REEL AD8009ART-REEL7 AD8009-EB
Temperature Range -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C
Package Description 8-Lead SOIC 13" Tape and Reel 5-Lead SOT-23 13" Tape and Reel 7" Tape and Reel Evaluation Board
Package Option SO-8 SO-8 RT-5 RT-5 RT-5 SO-8
Branding Information
HKJ HKJ HKJ
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD8009 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. B
-3-
AD8009-Typical Performance Characteristics
3 2 G = +1, RT 1
NORMALIZED GAIN - dB
6.2
G = +1, R
6.1 6.0
GAIN FLATNESS - dB
0 -1 -2 -3 -4 -5 -6 -7 1 10 100 FREQUENCY - MHz 1000 R PACKAGE: RL = 100 VO = 200mV p-p G = +1, +2: RF = 301 G = +10: RF = 200 RT PACKAGE: G = +1: RF = 332 G = +2: RF = 226 G = +10: RF = 191
5.9 5.8 5.7 5.6 5.5 5.4 5.3 5.2 1 10 100 FREQUENCY - MHz 1000 G = +2 RF = 301 RL = 150 VO = 200mV p-p
G = +2, R & RT G = +10, R & RT
Figure 4. Frequency Response; G = +1, +2, +10, R and RT Packages
Figure 7. Gain Flatness; G = +2
8 7 6 5
22 21 20 19 GAIN - dB
G = +2 RF = 301 RL = 150 VO AS SHOWN
4 3 2 1 0 -1 -2 1
18 17 16 15 14 13 12
4V p-p 2V p-p
G = +10 RF = 200 RL = 100 VO AS SHOWN
GAIN - dB
2V p-p
4V p-p
10 100 FREQUENCY - MHz
1000
1
10 100 FREQUENCY - MHz
1000
Figure 5. Large Signal Frequency Response; G = +2
Figure 8. Large Signal Frequency Response; G = +10
8 7 6 -40 C 5 GAIN - dB 4 3 2 1 0 -1 -2 1 10 100 FREQUENCY - MHz 1000 G = +2 RF = 301 RL = 150 VO = 2V p-p -40 C +85 C
22 21 20 19 -40 C +85 C
GAIN - dB
18 17 16 15 14 13 12 1
G = +10 RF = 200 RL = 100 VO = 2V p-p
+85 C
10 100 FREQUENCY - MHz
1000
Figure 6. Large Signal Frequency Response vs. Temperature; G = +2
Figure 9. Large Signal Frequency Response vs. Temperature; G = +10
-4-
REV. B
AD8009
-30 G=2 RF = 301 VO = 2V p-p 100 2ND, LOAD 3RD, 100 LOAD -80 3RD, 150 LOAD -90 -100 1 10 FREQUENCY RESPONSE - MHz 100 200 2ND, LOAD
-30 -35 -40 G = +10 RF = 200 RL = 100 VO = 2V p-p
-40
2ND
-50
DISTORTION - dBc
DISTORTION - dBc
-45 -50 -55 3RD -60 -65 -70 -75 -80 5 10 FREQUENCY - MHz 100 200
-60 150 -70
Figure 10. Distortion vs. Frequency; G = +2
Figure 13. Distortion vs. Frequency; G = +10
-35 -40 -45 70MHz
DISTORTION - dBc
-35 250MHz -40 -45 -50 -55 -60 -65 -70 -75 -80 -85 -90 -6 -4 -2 0 2 4 6 8 10 12 14 -95 -10 -8 -6 -4 -2 0 2 4
50 50 200 22.1 50 POUT
250MHz
-50 DISTORTION - dBc -55 -60 -65
200
70MHz
5MHz
5MHz
-70 -75
22.1
50 POUT 50
50
-80 -85 -10 -8
6
8
10
12
14
POUT - dBm
POUT - dBm
Figure 11. 2nd Harmonic Distortion vs. POUT; (G = +10)
Figure 14. 3rd Harmonic Distortion vs. POUT; (G = +10)
0.02
50
G = +2 RF = 301
DIFF GAIN - %
0.01 0.00 -0.01 -0.02
RL = 150
45
22.1
200 50 50 50 POUT
INTERCEPT POINT - dBm
40 35 30 25 20 15 10 10
RL = 37.5 0 IRE RL = 37.5 100
DIFF PHASE - Degrees
0.10
G = +2 0.05 RF = 301
-0.00 RL = 150 -0.05 -0.10 0 100
IRE
100 FREQUENCY - MHz
250
Figure 12. Differential Gain and Phase
Figure 15. Two Tone, 3rd Order IMD Intercept vs. Frequency; G = +10
REV. B
-5-
AD8009
1M 0
-10
301
-15
301 VIN = 200mVp-p 154 154 VO 100
100k
-20
GAIN
-40
TRANSRESISTANCE-
PHASE - Degrees
-25
CMRR- dB
-30 -35 -40 -45
10k
RL = 100
PHASE
-80
1k
-120
-50 -55
100 0.01
0.1
1
10
100
-160 1000
-60 1 10 100 FREQUENCY - MHz 1000
FREQUENCY - MHz
Figure 16. Transresistance and Phase vs. Frequency
Figure 19. CMRR vs. Frequency
10 0 -10 -20 G = +2 RF = 301 RL = 100 100mV p-p ON TOP OF VS 100 G = +2 RF = 301
OUTPUT RESISTANCE -
10
PSRR - dB
-30 -40 -50 -60 -70 0.03 0.1
-PSRR +PSRR
1
0.1
0.01 1 10 100 500 0.03 0.1 1 10 100 500
FREQUENCY - MHz
FREQUENCY - MHz
Figure 17. PSRR vs. Frequency
Figure 20. Output Resistance vs. Frequency
300
10
INPUT VOLTAGE NOISE - nV Hz
250
INPUT CURRENT - pA Hz
8
200
6
150
4
100 NONINVERTING CURRENT 50 INVERTING CURRENT 0 10 100 1k 10k 100k 1M 10M 100M 250M FREQUENCY - Hz
2
0 10
100
1k
10k
100k
1M
10M
100M 250M
FREQUENCY - Hz
Figure 18. Current Noise vs. Frequency
Figure 21. Voltage Noise vs. Frequency
-6-
REV. B
AD8009
25
-20 -30
20
-40
NOISE FIGURE - dB
G = +10 RF = 200
15 G = +10 RF = 301 RL = 100
S12 - dB
-50 -60 -70 -80
10
5
-90
0
1
10 100 SOURCE RESISTANCE -
500
1
10 100 FREQUENCY - MHz
1000
Figure 22. Noise Figure
Figure 25. Reverse Isolation (S12 ); G = +10
2.0
2.2
CCOMP 49.9 49.9 200
1.8
2.0 1.8 1.6 1.4
1.6
VSWR
1.4
VSWR
22.1
1.2
1.2
CCOMP = 0pF CCOMP = 3pF
1
1 0 0.1
0 0.1
1
10 FREQUENCY - MHz
100
500
1
10 FREQUENCY - MHz
100
500
Figure 23. Input VSWR; G = +10
Figure 26. Output VSWR; G = +10
20 18 16 G = +2 RF = 301
POUT MAX - dBm
14 12 10 8
RF
100 90
VOUT
G = +10 RF = 200 RL = 100
G = +10 RF = 200
VIN = 2VSTEP
6 4 2 0 5
RG
50 50
10
POUT
0%
50
2V
2V
250ns
10 FREQUENCY - MHz
100
250
Figure 24. Maximum Output Power vs. Frequency
Figure 27. Overdrive Recovery; G = +10
REV. B
-7-
AD8009
G = +2 RF = 301 RL = 150 VO = 200mV p-p
G = +10 RF = 200 RL = 100 VO = 200mV p-p
50mV
1ns
50mV
2ns
Figure 28. Small Signal Transient Response; G = +2
Figure 31. Small Signal Transient Response; G = +10
G = +2 RF = 301 RL = 150 VO = 2V p-p
G = +10 RF = 200 RL = 100 VO = 2V p-p
500mV
1ns
500mV
2ns
Figure 29. 2 V Transient Response; G = +2
Figure 32. 2 V Transient Response; G = +10
G = +2 RF = 301 RL = 150 VO = 4V p-p
G = +10 RF = 200 RL = 100 VO = 4V p-p
1V
1.5ns
1V
3ns
Figure 30. 4 V Transient Response; G = +2
Figure 33. 4 V Transient Response; G = +10
-8-
REV. B
AD8009
8 7 6 5 CA = 1pF 1 dB/div CA = 0pF 1 dB/div CA = 2pF 3 dB/div 12 9 6 3 ZOUT = 50 +5V ZIN = 50 HP8753D
GAIN - dB
GAIN - dB
4 3 2
VOUT = 200mV p-p
0 -3 -6 -9
0.001 F 2 49.9 3 4 301 7
0.1 F
+
10 F
AD8009
6
1 0
VIN 50 499 CA 499 100
49.9
VOUT
WAVETEK 5201 BPF
-12 -15 301
-1 1 10 100 FREQUENCY - MHz 1000
0.001 F -5V
0.1 F
10 F +
Figure 34. Small Signal Frequency Response vs. Parasitic Capacitance
Figure 36. AD8009 Driving a Bandpass RF Filter
0
CA = 2pF CA = 1pF VIN 50 CA 499 499 VOUT = 200mV p-p VS = 5V CA = 0pF VOUT 100
-10 -20 -30
REJECTION - dB
-40 -50 -60 -70 -80
AD8009 G=2 RF = RG= 301 DRIVING WAVETEK 5201 TUNABLE BPF fC = 50MHz
40mV
1.5ns
-90 CENTER 50.000 MHz SPAN 80.000 MHz
Figure 35. Small Signal Pulse Response vs. Parasitic Capacitance
APPLICATIONS
Figure 37. Frequency Response of Bandpass Filter Circuit
All current feedback op amps are affected by stray capacitance on their -INPUT. Figures 34 and 35 illustrate the AD8009's response to such capacitance. Figure 34 shows the bandwidth can be extended by placing a capacitor in parallel with the gain resistor. The small signal pulse response corresponding to such an increase in capacitance/ bandwidth is shown in Figure 35. As a practical consideration, the higher the capacitance on the -INPUT to GND, the higher RF needs to be to minimize peaking/ringing.
RF Filter Driver
Figure 36 shows a circuit for driving and measuring the frequency response of a filter, a Wavetek 5201 Tunable Band Pass Filter that is tuned to a 50 MHz center frequency. The HP8753D network provides a stimulus signal for the measurement. The analyzer has a 50 source impedance that drives a cable that is terminated in 50 at the high impedance noninverting input of the AD8009. The AD8009 is set at a gain of two. The series 50 resistor at the output, along with the 50 termination provided by the filter and its termination, yield an overall unity gain for the measured path. The frequency response plot of Figure 37 shows the circuit to have an insertion loss of 1.3 dB in the pass band and about 75 dB rejection in the stop band.
The output drive capability, wide bandwidth and low distortion of the AD8009 are well suited for creating gain blocks that can drive RF filters. Many of these filters require that the input be driven by a 50 source, while the output must be terminated in 50 for the filters to exhibit their specified frequency response.
REV. B
-9-
AD8009
75 IOUTR 75 RED 75 COAX PRIMARY MONITOR
ADV7160 ADV7162
IOUTG 75 GREEN 75
IOUTB 75 BLUE 75
5V + 0.1 F 3 7 10 F ADDITIONAL MONITOR 6 4 75 75 COAX RED 75
AD8009
2 301 301
0.1 F -5V
+
10 F
3
AD8009
2 301 301 3
6
75 GREEN 75
AD8009
2
6
75 BLUE 75
301
301
Figure 38. Driving an Additional High Resolution Monitor Using Three AD8009s
RGB Monitor Driver
High resolution computer monitors require very high full power bandwidth signals to maximize their display resolution. The RGB signals that drive these monitors are generally provided by a current-out RAMDAC that can directly drive a 75 doubly terminated line. There are times when the same output wants to be delivered to additional monitors. The termination provided internally by each monitor prohibits the ability to simply connect a second monitor in parallel with the first. Additional buffering must be provided. Figure 38 shows a connection diagram for two high resolution monitors being driven by an ADV7160 or ADV7162, a 220 MHz (Mega-pixel per second) triple RAMDAC. This pixel rate requires a driver whose full power bandwidth is at least half the pixel rate or 110 MHz. This is to provide good resolution for a worst case signal that swings between zero scale and full scale on adjacent pixels.
The primary monitor is connected in the conventional fashion with a 75 termination to ground at each end of the 75 cable. Sometimes this configuration is called "doubly terminated" and is used when the driver is a high output impedance current source. For the additional monitor, each of the RGB signals close to the RAMDAC output is applied to a high input impedance, noninverting input of an AD8009 that is configured for a gain of +2. The outputs each drive a series 75 resistor, cable and termination resistor in the monitor that divides the output signal by two, thus providing an overall unity gain. This scheme is referred to as "back termination" and is used when the driver is a low output impedance voltage source. Back termination requires that the voltage of the signal be double the value that the monitor sees. Double termination requires that the output current be double the value that flows in the monitor termination.
-10-
REV. B
AD8009
Driving a Capacitive Load
A capacitive load, like that presented by some A/D converters, can sometimes be a challenge for an op amp to drive depending on the architecture of the op amp. Most of the problem is caused by the pole created by the output impedance of the op amp and the capacitor that is driven. This creates extra phase shift that can eventually cause the op amp to become unstable. One way to prevent instability and improve settling time when driving a capacitor is to insert a resistor in series between the op amp output and the capacitor. The feedback resistor is still connected directly to the output of the op amp, while the series resistor provides some isolation of the capacitive load from the op amp output.
+5V G = + 2: RF = 301 = RG 0.001 F 7 0.1 F + 10 F G = + 10: RF = 200 , RG = 22.1 3 RT 49.9
Figure 39 shows such a circuit with an AD8009 driving a 50 pF load. With RS = 0, the AD8009 circuit will be unstable. For a gain of +2 and +10, it was found experimentally that setting RS to 42.2 will minimize the 0.1% settling time with a 2 V step at the output. The 0.1% settling time was measured to be 40 ns with this circuit. For smaller capacitive loads, a smaller RS will yield optimal settling time, while a larger RS will be required for larger capacitive loads. Of course, a larger capacitance will always require more time for settling to a given accuracy than a smaller one, and this will be lengthened by the increase in RS required. At best, a given RC combination will require about 7 time constants by itself to settle to 0.1%, so a limit will be reached where too large a capacitance cannot be driven by a given op amp and still meet the system's required settling time specification.
AD8009
2 4
6 2VSTEP
RS CL 50pF
RG
RF 0.001 F -5V 0.1 F + 10 F
Figure 39. Capacitive Load Drive Circuit
REV. B
-11-
AD8009
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
8-Lead SOIC (SO-8)
0.1968 (5.00) 0.1890 (4.80)
8 1 5 4
0.1574 (4.00) 0.1497 (3.80)
0.2440 (6.20) 0.2284 (5.80)
PIN 1 0.0098 (0.25) 0.0040 (0.10)
0.0688 (1.75) 0.0532 (1.35)
0.0196 (0.50) x 45 0.0099 (0.25)
SEATING PLANE
0.0500 0.0192 (0.49) (1.27) 0.0138 (0.35) BSC
0.0098 (0.25) 0.0075 (0.19)
8 0
0.0500 (1.27) 0.0160 (0.41)
5-Lead Plastic Surface Mount (SOT-23) (RT-5)
0.1181 (3.00) 0.1102 (2.80)
0.0669 (1.70) 0.0590 (1.50) PIN 1
5 1 2
4 3
0.1181 (3.00) 0.1024 (2.60)
0.0374 (0.95) BSC 0.0748 (1.90) BSC 0.0512 (1.30) 0.0354 (0.90) 0.0059 (0.15) 0.0019 (0.05) 0.0197 (0.50) 0.0138 (0.35) 0.0571 (1.45) 0.0374 (0.95) SEATING PLANE 10 0
0.0079 (0.20) 0.0031 (0.08)
0.0217 (0.55) 0.0138 (0.35)
-12-
REV. B
PRINTED IN U.S.A.
C2199-0-4/00 (rev. B)


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